Publications

2022

• C. Deutschbein, A. Meza, F. Restuccia, R. Kastner, & C. Sturton, “Isadora: automated information-flow property generation for hardware security verification”. Journal of Cryptographic Engineering, 2022.

• F. Restuccia, M. Pagani, A. Biondi, M. Marinoni and G. Buttazzo, “Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs,” in IEEE Transactions on Computers, vol. 72, no. 1, pp. 154-167, 1 Jan. 2023, doi: 10.1109/TC.2022.3214117.

• F. Restuccia, A. Meza, R. Kastner and J. Oberg, “A Framework for Design, Verification, and Management of SoC Access Control Systems,” in IEEE Transactions on Computers, vol. 72, no. 2, pp. 386-400, 1 Feb. 2023, doi: 10.1109/TC.2022.3209923.

• G. Sciangula, F. Restuccia, A. Biondi and G. Buttazzo, “Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC,” 2022 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Spain, 2022, pp. 406-414, doi: 10.1109/DSD57027.2022.00061.

• F. Restuccia and R. Kastner, “Cut and Forward: Safe and Secure Communication for FPGA System on Chips,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4052-4063, Nov. 2022, doi: 10.1109/TCAD.2022.3197343.

• A. Meza, F. Restuccia, R. Kastner, & J. Oberg “Safety verification of third-party hardware modules via information flow tracking” In Proc. 1st Real-Time Intell. Edge Comput. Workshop (RAGE) Co-Located 59th Design Autom. Conf.(DAC) (pp. 1-4).

• R. Kastner, F. Restuccia, A. Meza, S. Ray, J. Fung, and C. Sturton. 2022. “Automating hardware security property generation”, In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC ‘22). Association for Computing Machinery, New York, NY, USA, 1384–1387. https://doi.org/10.1145/3489517.3530637

• G. Serra, P. Fara, G. Cicero, F. Restuccia and A. Biondi, “PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms,” 2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS), Milano, Italy, 2022, pp. 241-253, doi: 10.1109/RTAS54340.2022.00027.

• C. Deutschbein, A. Meza, F. Restuccia, M. Gregoire, R. Kastner and C. Sturton, “Toward Hardware Security Property Generation at Scale,” in IEEE Security & Privacy, vol. 20, no. 3, pp. 43-51, May-June 2022, doi: 10.1109/MSEC.2022.3155376.

• F. Restuccia, M. Pagani, A. Mascitti, M. Barrow, M. Marinoni, A. Biondi, G. Buttazzo, R. Kastner, “ARTe: Providing real-time multitasking to Arduino”, Journal of Systems and Software, Volume 186, 2022.

2021

• F. Restuccia and A. Biondi, “Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms,” 2021 IEEE Real-Time Systems Symposium (RTSS), Dortmund, DE, 2021, pp. 441-454, doi: 10.1109/RTSS52674.2021.00047.

• C. Deutschbein, A. Meza, F. Restuccia, R. Kastner, and C. Sturton. 2021. Isadora: Automated Information Flow Property Generation for Hardware Designs. In Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security (ASHES ‘21). Association for Computing Machinery, New York, NY, USA, 5–15. https://doi.org/10.1145/3474376.3487286

• F. Restuccia, A. Meza and R. Kastner, “Aker: A Design and Verification Framework for Safe and Secure SoC Access Control,” 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Munich, Germany, 2021, pp. 1-9, doi: 10.1109/ICCAD51958.2021.9643538.

• M. Barrow, F. Restuccia, M. Gobulukoglu, E. Rossi and R. Kastner, “A Remote Control System for Emergency Ventilators During SARS-CoV-2,” in IEEE Embedded Systems Letters, vol. 14, no. 1, pp. 43-46, March 2022, doi: 10.1109/LES.2021.3107837.

2020

• F. Restuccia, A. Biondi, M. Marinoni, G. Cicero and G. Buttazzo, “AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC,” 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2020, pp. 1-6, doi: 10.1109/DAC18072.2020.9218652.

• F. Restuccia, A. Biondi, M. Marinoni and G. Buttazzo, “Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC,” 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Fayetteville, AR, USA, 2020, pp. 129-137, doi: 10.1109/FCCM48280.2020.00026.

• F. Restuccia, M. Pagani, A. Biondi, M. Marinoni, and G. Buttazzo “Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs”. In 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020).

2019 and before

• F. Restuccia, M. Pagani, A. Biondi, M. Marinoni, and G. Buttazzo. “Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs.”” ACM Transactions on Embedded Computing Systems 18, 5s, Article 51 (October 2019), https://doi.org/10.1145/3358183

• A. Grossi, L. Zuolo, F. Restuccia, C. Zambelli and P. Olivo, “Quality-of-Service Implications of Enhanced Program Algorithms for Charge-Trapping NAND in Future Solid-State Drives,” in IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 363-369, Sept. 2015, doi: 10.1109/TDMR.2015.2448108.